Digital Logic Design MSc IT 1st Term Past paper 2018 UOS
University of Sargodha
M.Sc. 1st Term Exam 2018
Subject: I. T
Paper: Digital Logic Design (CMP: 2210)
Time Allowed: 2:30 Hour
Maximum Marks: 80
Objective Part (Compulsory)
Q.1. Write short answers of the following in 2–3 lines each. (2×16)
i. Simplify the expression, y = A B̅ D̅ + A B̅ D
ii. Convert (603)₁₀ into hexadecimal number.
iii. Give brief description of negative-AND gate.
iv. Implement Half Subtractor with logic diagram.
v. Convert (F₁₆)₁₆ into Octal.
vi. Explain how an Exclusive-NOR gate can be used to compare two binary bits?
vii. State and provide basic concept of Multiplexer.
viii. Show 786 in weighted code 5043210.
ix. In what conditions Tabulation method is better than Boolean Algebra?
x. Convert the following binary numbers: (i) 0111 (ii) 1111 to Gray code.
xi. Simplify to minimum number of literals: (x + ȳ)(x + y)
xii. Find 2’s complement, where most significant bit is a sign bit (1011110101)₂.
xiii. Draw the gate implementation using AND, OR, NOT gates of the function:
A · (B + C) · (A + E)
xiv. Obtain expression in POS: F(A, B, C, D) = ∏(0, 1, 2, 3, 4, 6, 8, 11, 12, 15)
xv. Prove (x + y)² = x + y by truth table.
xvi. Draw diagram of SR-Latch using NAND-gates.
Subjective Part (16×3)
Q.2. Implement the following by using multiplexer by taking B as input A, C, D as a selection line.
F = ∏(0,1,2,3,4,5,6,7,8,9,10,11)
Q.3. Explain the basic operation along with truth table of JK flip flop.
Q.4. Design the combinational logic circuit that gets 3-bit number as input and delivers the output equals to the cube of the input value.
Q.5. You are requested to make a telephone exchange for a single house. A house contains 8 rooms (8 extensions). Telephone exchange should be able to allow communication among 8 extensions. However 9th slot is available for PTCL. If a person dials on 9th slot and after that it must dial an extension number of required room, a call must be transferred to the required room.
Q.6. Construct a 5 x 32 decoder with four 3 x 8 decoders / de-multiplexers and a 2 x 4 decoder.
Use a block diagram construction.