Digital Logic Design MSc IT 1st Term Past paper 2015 UOS
University of Sargodha
Subject: MScIT
Course: Digital Logic Design (CMP-2210)
Time Allowed: 2.30 Hours
Maximum Marks: 80
1st Term Exam 2015
Q1. Note: Attempt all questions; each question carries equal marks? (16 x 2 = 32)
- Simplify the expression: $ y = A \cdot B + A \cdot B \cdot D $
- Convert $ (603)_{10} $ into hexadecimal number.
- Give brief description of negative-AND gate.
- Implement half subtractor with logic diagram.
- Convert $ (F)_{16} $ into Octal.
- Explain how an Exclusive-NOR gate can be used to compare two binary bits?
- State and provide basic concept of Multiplexer.
- Show $ 786 $ in weighted code $ 504320 $.
- In what conditions Tabulation method is better than Boolean Algebra?
- Convert the following binary numbers:
- to Gray code.
- Simplify to minimum number of literals: $ (x + y’)(x + y) $
- Find $ Z’ $ complement, where most significant bit is a git $ (101110110110) $.
- Draw the gate implementation using AND or NOT gates of the function:
- Obtain expression in POS: $ F(A, B, C, D) = \sum(10, 1, 2, 3, 4, 6, 8, 11, 12, 15) $.
- Prove the $ (x + y) = y + x $ by truth table.
- Draw diagram of SR-Latch using NAND-gates.