Digital Logic Design BS IT 2nd Term Past paper 2016 UOS

University of Sargodha

BS 2nd Term Examination 2017

• Subject: I. T
• Paper: Digital Logic Design (CMP:2210)
• Time Allowed: 2:30 Hours
• Maximum Marks: 80

Objective Part (Compulsory)

Q1. Write short answers of the following in 2-3 lines each. (2*16)

1. Show 5172 in weighted code 2421 in a 16 cell register.
2. In what conditions Quine-McCluskey method is better than K-map.
3. Multiply following binary numbers: 101101 by 110.
4. Simplify to minimum number of literals: .
5. Find 9’s complement of 125.639.
6. Draw the gate implementation using AND or OR gates of the function: .
7. Obtain expression in POS: .
8. Prove the  by truth table.
9. Simplify it to minimum number of literals: .
10. Convert  into hexadecimal number.
11. Convert  into binary number.
12. Implement NOT, OR and AND by using NAND gates.
13. Implement half subtractor with logic diagram.
14. Convert  into binary number.
15. Express the function of Exclusive-OR using 4 variables K-map.
16. Draw the logic diagram of D-Flip Flops using NAND gates.

Subjective Part (16*3)

Q2. Design a counter with the following binary sequence: 0, 1, 2, 3, 4, 5, 6, 7 and repeat. Use RS flip flops.

Q3. Design a BCD counter with JK Flip-Flops.

Q4. Implement the Boolean function using NAND gates:
$ F = B’D’ + A’C/D + AB/C’D + A/BC/D $

Q5. Construct a 5×32 decoder with four 3×8 decoders / demultiplexers and a 2×4 decoder. Use a block diagram construction.

Q6. Design a combinational circuit whose input is a four bit number and whose output is the 2’s complement of the input number.